NAT-MCH-PHYS80
- Designated for high demands regarding bandwidth, timing, and precision
- Specialized NAT-MCH-CLK-PHYS mezzanine module
- Power and system management for up to 12 AMCs, 2 CUs, and 4 PMs
- PCIe Gen3 x16 data switching towards backplane and front uplink
- RTM with COMExpress Support
NAT-MCH-CLK
- Support for AMC clocks CLK1, CLK2, and CLK3 for up to 12 AMCs, Update clock for 2nd NAT-MCH
- Variable switching and distribution of clocks by on-board FPGA
- Stratum 3 type PLL clock source for telecom applications
- Reference for Stratum 3 PLL can be either CLK1 or CLK2 from any AMC, or sourced from the front panel reference clock I/O
- PCI Express compliant clock signal can be distributed via CLK3 to all 12 AMCs
NAMC-psTimer
- Trigger synchronization with jitter of approx. 10ps
- Numerous programmable receiver outputs
- 2x trigger / 1x precision clock towards front panel as LVDS signals via RJ45
- Optional mezzanine and RTM for increased number of I/O
- Data word and table distribution via fiber links
NAMC-psTimer-RTM
- RF-Trigger connection to RTM backplane
- Programmable delay line
- 3x RJ45 at Rear Panel for differential signal distribution
- 9x Lemo connectors at Rear Panel for single-ended signal distribution
- 3 channels with 5ps solution
NAMC-PTM
- Features VCOCXO and VCTCXO
- Detection of internal or external clocking sources
- Quality rating of clocking signals
- Clock I/O at front panel via BNC connectors
- Operation in standard AMC- or dedicated PTM slot (if supported by Backplane)
NAT-AMC-TCK7
- Xilinx Kintex-7 FPGA
- Xilinx Coolrunner-II CLPD
- 8x 10 Gbps SFP+ interfaces towards the front panel
- Low-latency communication links to backplane and to RTM
- Clock distribution circuit with a broad range of reference frequencies for high-speed serial interfaces
NAT-MCH-CLK-PHYS
- Two direct low-jitter multiplexer connections with low latency
- CLK1 and CLK2 connections for all 12 AMC multiplexed by one device
- PCIe reference clock distribution for 12 AMCs via CLK3 (AMC.0 R2.0 – FCLKA)
- Variable switching and distribution of clocks by on-board FPGA
