NAT-MCH-CLK-PHYS

The NAT-MCH-CLK-PHYS is a spezialized low-jitter clock module for physics applications. It features low-jitter clock signal switching and distribution as well as PCIe reference clock generation. The onboard FPGA offers variable switching and distribution of clocks.

A special low-jitter clock multiplexer together with a programmable low-jitter oscillator provides very low-jitter and low-latency CLK1 and CLK2 signals. Moreover, the NAT-MCH-CLK-PHYS provides a Spread Spectrum or fixed 100 MHz PCIe clock (HCSL).

At the front panel, the module offers two CLK Inputs / Outputs via SMA connectors. All CLK1 and CLK2 signals are bi-directional, so if configured as output, the internal clock is accessible for external devices. If set up as input, the incoming clock signal can be processed by the FPGA or forwarded to the AMCs or a HUB-Module. One of the I/Os always connects directly to the FPGA, the other one can on customer demand be routed directly to the multiplexer (assembly option).

As the low-jitter clock module basically targets on physics applications, it comes along with the double-width NAT-MCH-PHYS80 by default. Nevertheless, the NAT-MCH-CLK-PHYS fits perfectly on the single-width NAT-MCH as well. This may be an option for other tasks requiring high-quality clock signals e.g., research & development or telecommuncation.

• CLK1 connections for all 12 AMC multiplexed by one device
• CLK2 connections for all 12 AMC multiplexed by one device
• Support of update CLK1 and CLK3 for a second NAT-MCH in a redundant system
• Two front panel reference clock I/O
• Two direct multiplexer interconnections
• Fixed low jitter reference clock
• Clock signals can be distributed over all backplane
• PCIe compliant clock signal can be distributed via CLK3 to all 12 AMCs